Every once in a while I read through the employment listings as part of the Semiconductor Manufacturing group on LinkedIn because I find it fascinating to see what employers are looking for even if I am not applying.
Particularly for verification engineering position, one of the job responsibilities typically includes development of the architecture for a functional verification environment including reference models, bus functional monitors and drivers. I saw three positions that called for this. Then, I noted that S3 Group is looking for a senior RF/analog/mixed-signal design engineer that requires the candidate to have experience in die-size estimation and modeling of the trade-offs between functionality and die-size and package selection. No matter what part of the design chain, there is a need for modeling.
IBM Fellow Charles Webb explained his group does quite a bit of power modeling. “Starting with the models that we get from the technology development group that’s doing the process development and we feed those models into our own design tools to get a static estimate. We also make use of the performance models that we have to keep track of how much is happening, where. We use those to model the clock gating efficiencies. Like all designs now we employ local clock gating so that we’re not switching transistors or units that aren’t doing anything that cycle. So we use the performance models, running against traces of real workloads so we can get an idea of how effective that is and how to spend that resource of doing the clock gating effectively to cut down the max real world power that we worry about. That’s much more the concern for us than average power.”
He also said it is nice that the power goes down when doing less but the real constraint that his team is under is that they need to be able to run the mainframe systems they design fully configured, running 90-95% utilization, since that is how many customers run their systems on a sustained basis.
“They have to provision enough power for the system there and we can’t be throttling performance under those circumstances because that’s exactly where they need it. We really design for not so much the absolute maximum because we know that that actually is not generally attainable – we have to build backstops, we make sure that we stay within our limits but really we’re designing for a maximum sustainable power and be able to do that without any throttling and sustain that steady. We use the performance models to see how we’re doing on the clock gating, we have extensive physical modeling of the circuits that feeds into our physical design tools and that then becomes one of the real challenges for the designers,” Webb added.
Of course, not all companies have the robust design engineering and verification teams that one of the last remaining IDMs does, which is why is makes sense to look to industry standard modeling techniques for the way ahead. Before you argue that the standardization path is fraught with problems, it is a good starting point for many design and verification engineers. But if you have a better suggestion, please let me know!
–Ann Steffora Mutschler
